In some types of communications systems, a transmitter converts a sequence of data symbols into multiple serial data streams and transmits the serial data streams over multiple data lanes to a receiver by using a transmit clock signal. The receiver reconstructs the transmit clock signal of the transmitter for each data stream, converts data in each data stream into data symbols based on the reconstructed clock signal of the data stream, and stores the data symbols of each data stream into a corresponding elastic buffer based on the reconstructed clock signal of the data stream. Although the reconstructed clock signals have the same average frequency as the transmit clock signal over a sufficiently long time period, the frequency of each reconstructed clock signal may independently drift away from the average frequency in shorter time periods because of changing conditions in the data lanes.
Because of the frequency variations in the reconstructed clock signals, the data rates of the data streams may differ over shorter time periods. To compensate for the different rates of the data streams, the transmitter periodically inserts a skip ordered set containing control symbols into each data steam. In turn, the receiver selectively adds or deletes control symbols in the skip ordered sets, as is appropriate, and stores each skip ordered set of a data stream into the elastic buffer corresponding to the data stream. Further, the receiver reads data symbols of each data stream from the elastic buffers and stores the data symbols of each data stream into a corresponding deskew circuit by using a receiver clock signal. The frequency of the receiver clock signal is approximately the same as the frequency of the transmit clock signal but has an average frequency that may differ slightly from the average frequency of the transmit clock signal. Because of different propagation delays in the receiver (e.g., static skew) and as a result of the receiver adding or deleting control symbols in skip ordered sets (e.g., dynamic skew), the data symbols stored in the deskew circuits may be misaligned from each other. Nonetheless, the receiver aligns the data symbols stored in the deskew circuits based on the receiver clock signal and reconstructs the sequence of data symbols from the aligned data symbols.
In some communication systems, each of the deskew circuits receives one symbol per clock cycle and is capable of deskewing one symbol per clock cycle. In other communication systems, each of the deskew circuits receives a pair of symbols per clock cycle and is capable of deskewing two symbols per clock cycle. In these communication systems, design and manufacture of the receiver is complicated by wire interconnects in the deskew circuits and wire interconnects between the elastic buffers and the deskew circuits. In particular, the number of wire interconnects needed for receiving and deskewing a pair of symbols per clock cycle is substantially greater than the number of wire interconnects needed for receiving and deskewing a single symbol per clock cycle. As a result, routing the wire interconnects in the receiver takes a considerable amount of time in a design cycle of the receiver and has a higher likelihood of creating timing problems late in the design cycle. Moreover, the receiver is typically implemented in a semiconductor chip and the wire interconnects consume a considerable amount of die area and power in the semiconductor chip.
In light of the above, a need exists for an improved system and method for deskewing multiple symbols of a data stream in a clock cycle. A further need exists for reducing the design cycle of a receiver capable of receiving and deskewing multiple symbols of a data stream in a clock cycle. An additional need exists for reducing size and power consumption of deskew circuits capable of receiving and deskewing multiple symbols of a data stream in a clock cycle.